Hierarchical Formal Verification Method based on Transactions
نویسندگان
چکیده
Complexity and large scale of SoC designs call for developments in today’s verification techniques. On the one hand, it costs too much efforts and time in traditional RTL modeling methodologies when verifying large scale designs; on the other hand, properties requiring cycle accuracy are not efficiently verified in Transaction Level Models due to the abstraction. In this paper, we present a hierarchical verification methodology which is dedicated to make tradeoffs between verification efficiency and completeness. Design under Verification (DUV) is firstly abstracted based on transactions; refinements on them will be done later in verification flow only when verifying properties which require finer time accuracy. Furthermore, improvements on model checking techniques are also proposed.
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تاریخ انتشار 2009